To extend battery life and reduce power consumption, microprocessors for mobile use may have various power modes, such as a stop-clock mode and an active mode. The microprocessor is put in its active mode when its execution units are needed, and is put in its stop-clock mode when the execution units are not immediately needed. To conserve power, the microprocessor draws less current during its stop-clock mode than during its active mode.
A DC-to-DC voltage converter provides a regulated voltage for the microprocessor. FIG. 1 is a functional diagram of a step-down switching DC-to-DC voltage converter connected to a microprocessor, where the microprocessor is idealized as current sink 102. Microprocessor 102 sinks current I, which varies depending upon whether microprocessor 102 is in its stop-clock or active mode. The voltage to be regulated is the voltage at node 110 and, ignoring voltage drops along line 111, is the core voltage of microprocessor 102, denoted as V.sub.core. A voltage source 104 provides a stable reference voltage, denoted as V.sub.0, to controller 106. Feedback path 108 samples the voltage at node 110.
Controller 106 switches FETs (Field Effect Transistor) 112 and 114 ON and OFF in complementary fashion so as to energize and de-energize inductor 116. FETs 112 and 114 should be switched so as not to be simultaneously ON. Controller 106 switches FET 114 OFF and FET 112 ON to raise the voltage at node 110, and switches FET 112 OFF and FET 114 ON to lower the voltage at node 110. Capacitor 118 helps to smooth-out the voltage at node 110. Resistor 120 represents the parasitic resistance of capacitor 118 and its lead. Not shown is the parasitic inductance of capacitor 118 and its lead. By appropriately switching FETs 112 and 114, the voltage at node 110 is regulated to be substantially constant provided microprocessor 102 is not changing modes.
FIG. 2a illustrates ideal transitions of current I due to microprocessor 102 changing modes, and FIG. 2b illustrates the voltage V.sub.core at node 110 due to these current transitions. For the example of FIG. 2a, current I increases at time t.sub.1 due to a mode change from stop-clock to active, and decreases at time t.sub.2 due to a mode change from active to stop-clock. Let V.sub.r denote the desired voltage for V.sub.core. (V.sub.r will also be referred to as the set-point.) When current I undergoes a sudden increase at time t.sub.1, the current flowing through inductor 116 cannot increase instantaneously, and consequently the additional current needed by microprocessor 102 is supplied from capacitor 118. This additional current increases the magnitude of the voltage drops across resistor 120 and capacitor 118, which causes the voltage V.sub.core at node 110 to suddenly decrease. To bring V.sub.core up to V.sub.r, control circuit 106 keeps FET 112 ON and FET 114 OFF. The current flowing through inductor 116 will then increase (with positive time derivative) to bring V.sub.core to V.sub.r. This is illustrated in FIG. 2b at time t.sub.1.
Similarly, when microprocessor 102 changes from its active mode to its stop-clock mode at time t.sub.2, current I suddenly decreases. Again, because current flow through inductor 116 cannot decrease instantaneously, capacitor 118 must sink additional current, This causes a sudden increase in V.sub.core at time t.sub.2, which is eventually brought down to V.sub.r by keeping FET 112 OFF and FET 114 ON. This is illustrated in FIG. 2b at time t.sub.2.
As a result of microprocessor 102 changing modes, the voltage at node 110 varies between some maximum or peak voltage V.sub.p and some minimum voltage V.sub.m. For simplicity, we assume that the voltage differences .vertline.V.sub.p -V.sub.r .vertline. and .vertline.V.sub.m -V.sub.r .vertline. are equal to each other, and we denote this difference by A. Note that the total voltage excursion for FIG. 2b, .vertline.V.sub.p -V.sub.m .vertline., is equal to 2.DELTA..
The value of A depends upon the time derivative of current during a mode change, the values of resistor 120 and capacitor 118 (and any parasitic inductance not explicitly shown), the value of inductor 116, and how quickly controller 106 responds to a changing core voltage. A larger inductor 116 and capacitor 118 reduces steady state ripple in the core voltage when there is no power mode change, but increases .DELTA.. For proper operation, V.sub.p and V.sub.m need to be within some operating range [V.sub.low, V.sub.high ].
Clearly, tradeoffs can be made between voltage ripple, response time, and .DELTA.. However, once such a tradeoff has been made, it is desirable to keep the total voltage swing .vertline.V.sub.p -V.sub.m .vertline. as small as possible. This is particularly important in low voltage applications, where the set-point V.sub.r should be as low as needed without V.sub.m dropping below V.sub.low.